TTO_Grant Catalogue Grant Catalogue | Page 13

Synthesis of Clock Trees for Sampled-Data Analog IC Blocks It is obvious that automated design of clock (buffer-cell) network of SDACs would eliminate the possibility of error, reduce development time, and allow analog IC design engineers to focus their attention on parts of the design that need creativity. The claim of our project is that we are indeed able to automate the design of SDAC clock distribution circuits by writing an extra software layer that runs on top of (digital) CTS software. The deliverables of our project were a methodology and a software. The methodology deliverable is also useful in the case of manual design. Software deliverable of the project (called ACTreS for Analog Clock Tree Synthesis), on the other hand, synthesizes the circuit as well as the layout of clock distribution network. ACTreS does so by driving an already existing CTS software (in multiple runs) with constraint files it automatically generates. We successfully validated our methodology and ACTreS software for the design of a 10-bit 0.18 micron 60 MHz 2-step Flash differential-input ADC circuit as a test case. Yrd. Doç. Dr. Hasan Fatih Uğurdağ DEPARTMENT Electrical & Electronics Engineering CONTACT [email protected] FUNDING SCHEME TÜBİTAK 1001 START DATE 01.10.2010 DURATION 24 months 2010 National Grants This project aimed to develop a methodology for automated design of clock trees in Sampled-Data Analog Circuits (SDACs). The current practice in the industry and academia for clock tree design of SDACs is a manual process, which is timeconsuming and error-prone. Clock tree design in digital domain, however, is fully automated and is carried out by what we call Clock Tree Synthesis (CTS) software. In spite of some critical differences, SDAC clock tree design problem has fundamental similarities with its digital counterpart. Therefore, this work started with the question of “Why don’t we use CTS software for analog circuits while we are able to utilize them successfully for digital?” Electrical & Electronics Engineering ABSTRACT OZU BUDGET 147,187.00 TL 13