In Conversation
design environments to greatly simplify programming and
increase productivity. The high end of the UltraScale+ portfolio
leverages the combined power of 3D transistors and 3rd
generation of Xilinx 3D ICs. Just as FinFETs enable a non-linear
improvement in performance/watt over planar transistors, 3D ICs
enable a non-linear improvement in systems integration and
bandwidth/watt over monolithic devices.
Built from the ground up for Xilinx’s 28nm portfolio, the Vivado
Design Suite has been co-optimized with the UltraScale
architecture to deliver significant quality of results, routability,
utilization, and productivity advantages. When combined with
UltraFast, a potent methodology that covers all aspects of board
planning, design creation, design implementation and closure,
programming and hardware debug, design teams will be able to
accelerate their time to predic table success.
Productivity for the front end design process is multiplied by
more than 4X with high level synthesis and IP integration tools.
Productivity in design implementation improves by more than 4X
due to faster hierarchical planning and analytic place and route
engines as well as support for fast incremental ECOs.
Two years ago Xilinx launched the SDx Development
Environments for Embedded Computing. The SDAccel and SDSoC
Environments offer GPU-like and familiar embedded application
development and runtime experiences for C, C++ and/or OpenCL
development, while the SDNet Environment enables networking
engineers to create high performance programmable data plane
designs. All these platforms are available with support for a
variety of Xilinx and third party boards, libraries and tools.
Xilinx's embedded runtime development environments and tools
include comprehensive training and support for developing your
ARM or Micro Blaze based platforms. You have access to the
debuggers, compilers and other tools you need as well as
complete Linux and Multi-OS environments. These embedded
runtime environments target multiple boards using readily
available reference designs and libraries with development
support from videos, Github, Wiki, and other open source
resources.
ELE Times: Briefly describe the role of FPGA in powering High
Performance Computing?
Giles Peckham: Today, both commercial and academic HPC
computing sitesneed enormous performance to process
increasingly complex algorithms on larger data sets while
achieving greater energy efficiency.
Computing platforms based on Xilinx FPGAs enable up to 25X
better performance/watt for data center applications than CPUonly servers. The SD Accel development environment combines
the industry's first architecturally optimizing compiler supporting
any combination of OpenCL, C, and C++ kernels, along with
libraries, development boards and the first complete CPU/GPU
like development and run-time experience for FPGAs.
ELE Times: Please explain the necessity of FPGA and its use in
Data Centers, 5G wireless and cloud.
Giles Peckham: Data centers need to be workload optimized so
they can adapt to rapidly changing throughput, latency, and
power requirements from a wide range of large scale, virtualized
applications. These applications include machine learning, video
transcoding, and big data analytics, along with storage and
networking.
Through workload optimization, Xilinx can enable servers to
deliver 10X the throughput with one tenth the latency relative to
CPU based alternatives. Applications are written in a mix of
languages that include OpenCL, C, and C++. Only Xilinx provides a
flexible, standards-based solution that combines software
programmability, workload optimization, and high performance
data center interconnect with the security needed for the next
generation of cloud computing.
Xilinx's All Programmable portfolio includes UltraScale technology
that serves as a scalable reconfigurable acceleration platform that
can be optimized on demand to any workload. Xilinx's software
defined development environment, SDAccel, enables customers
to quickly develop their unique applications using any mix of
OpenCL, C, and C++. SDAccel deploys a unique architecturally
optimized compiler and partial reconfiguration technology that
together offer the highest quality of results with a flexible runtime
capability. Furthermore, Xilinx announced recently the expansion
of its 16nm UltraScale+ product roadmap with new acceleration
enhanced technologies for the Data Center. The resulting
products will deliver the powerful combination of Xilinx's
industry-leading 16nm FinFET+ FPGAs with integrated HighBandwidth Memory (HBM), and support for the recently
announced Cache Coherent Interconnect for Acceleration
technology (CCIX). CCIX is initially driven by a group of seven
companies to enable an acceleration framework that works with
multiple processor architectures. These acceleration enhanced
technologies will enable efficient heterogeneous computing for
the most demanding data center workloads. The new products
will also be highly leveraged in many other compute intensive
applications requiring high memory bandwidth.
Built on TSMC’s proven CoWoS process, Xilinx HBM-enabled
FPGAs will improve acceleration capabilities by offering 10X
higher memory bandwidth relative to discrete memory channels.
HBM technology enables multi-terabit memory bandwidth
integrated in package for the lowest possible latency. To further
optimize data center workloads, the new CCIX technology
promotes efficient heterogeneous computing by allowing
processors with different instruction-set architectures to
coherently share data with accelerators such as the Xilinx HBMenabled FPGAs.
Xilinx is collaborating with leading hyperscale data center
customers to create accelerated servers customized and
optimized for their workloads.
Errata- Rohde & Schwarz Looking forward to a healthy manufacturing eco-system in India
We express our apology to Mr. Yatish Mohan, Managing Director, Rohde & Schwarz India, for typographical error in an article
“Rohde & Schwarz Looking forward to a healthy manufacturing eco-system in India”. The mistake is unintentional and nothing else.
From ELE Times, October 2016 issue — "In our special story of Rohde & Schwarz Looking forward to a healthy manufacturing ecosystem in India (Page 63 and 64), we wrote “Rhode & Schwarz”. In fact, it should be read as “Rohde & Schwarz” on both the pages.
ELE Times | 60 | November, 2016