SuperFlash technology changed the |
endurance for these applications . |
memory block tend to have tail bits which |
industry with its differentiated and |
pose difficulties in reading accuracy . |
Embedded Flash Memory is |
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Scalable |
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Embedded Flash can work at Low
Voltages for IoT applications
IoT applications require low-voltage read / write operation . Even though
Program / Erase operation needs high voltage , it is transparent to the user as the flash macro receives core / IO voltage from the user and uses an internal charge pump to raise the voltage to the required high voltage for Program and Erase operation .
Therefore , embedded flash is ready for low-power IoT applications .
Embedded Flash supports
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Ten years ago , the word on the street was that embedded flash was dead at sub-
90nm nodes because of the perceived difficulty and challenges in scaling the bitcell . That perception has been proven wrong now as embedded flash is already in development at 28nm . The challenge today is to scale embedded flash to FinFet process generations . There are however , foundries such as Samsung and Global
Foundries focusing on FDSOI technology on planar 22nm technology nodes and possibly beyond which may extend the life of embedded flash beyond the 28nm
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nodes . In 2012 , embedded flash at pureplay foundries was only available at 90nm .
But , in the last four years , embedded flash availability is reaching 28nm at many leading foundries ( Figure 1 ) and in development for high-end automotive and
IoT solutions . This huge leap in development was primarily driven by automotive applications , which are driving the demand of automotive MCUs on advanced technology nodes .
Automotive , mobile and IoT applications
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EEPROM functionality |
node . |
Traditional EEPROM architecture |
Embedded Flash can not be |
supported Byte-write operation and was |
replaced by OTP for Instruction |
used by applications requiring frequent |
Code Applications |
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data updates . Generally , embedded flash is organized in a group of cells called sectors . A sector needs to fully Erased before new data can be written . However , there are simple design techniques using an SRAM buffer that can be used to mimic
EEPROM functionality at a fraction of the overall embedded flash memory area , and would be transparent to the user .
A frequent misconception is that embedded flash can ’ t meet EEPROM endurance . However , an EEPROM can typically meet 1M endurance cycles .
Historically most of the MCU and smartcard applications required less than
100K endurance , though recently more stringent requirements for some applications such as SIM cards have pushed endurance requirements to 500K endurance ( typical ). In support of this
requirement , the third generation
SuperFlash technology ( ESF3 ) has better endurance characteristics than its predecessor technologies and with plenty of data showing that it can meet 500K
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Some integrated circuits need to be programmed with an on-chip instruction code only once and this programming can be done either during wafer-sort or inpackage during final testing before shipping the integrated circuit to the client or can be done in-field . Although the one- time programming requirement of the non-volatile memory appears to be adequately satisfied with an OTP solution , in practice it has some serious user- experience and reliability issues . First , OTP programming for a large memory block is fraught with intractable low-yield challenges which requires use of multiple redundant bits and associated redundancy management circuitry . This added complexity is a headache for chip designers . Second , a large block of OTP solution in general doesn ’ t offer data- retention time that is competitive with that offered by a specialized embedded flash process optimized for long term data reliability . This is because the uncontrolled programming variations on a large OTP |